A Shallow Trench Isolation (STI) method is used as an element separation method in a semiconductor device for the purpose of high integration therein. FIGS. 1A through 1D illustrate cross sectional views accounting for element separation by an STI method in accordance with a first conventional embodiment. As shown in FIG. 1A, a pad oxide film 12 and a silicon nitride film 14 are formed on a silicon semiconductor substrate 10. An opening portion 22 is formed in a region of the pad oxide film 12 and the silicon nitride film 14 where a trench is to be formed in the substrate 10.
As shown in FIG. 1B, the semiconductor substrate 10 is subjected to an etching process using the silicon nitride film 14 as a mask, and a trench 20 is formed in the semiconductor substrate 10. As shown in FIG. 1C, the semiconductor substrate 10 inside the trench 20 is oxidized by thermal oxidation, and a trench oxide film 18 connecting to the pad oxide film 12 is formed. As shown in FIG. 1D, a silicon oxide film acting as an insulating film 30 is formed on the trench oxide film 18 in the trench 20.
As shown in FIG. 2A, the silicon nitride film 14 is removed and, as shown in FIG. 2B, the pad oxide film 12 is also removed with an overall etching process. When the pad oxide film 12 is etched, an upper portion of the insulating film 30 is also etched. Thus, an insulating layer 34 implanted in the trench 20 is formed from the trench oxide film 18 and the insulating film 30, thereby enabling a STI separation.
In the first conventional embodiment, in FIG. 1C, there may be generated a bird's beak on the trench 20 side at an interface between the silicon nitride film 14 and the semiconductor substrate 10 during the formation of the trench oxide film 18. As a result, a face of the semiconductor substrate 10 at the upper portion of the trench 20 may be inclined, as is case of a region 24. And as shown in FIG. 2B, an end portion of the insulating layer 34 and an end portion of the trench 20 in which the bird's beak is generated are overlapped with each other during the formation of the insulating layer 34 of the STI. And, the etching may be performed in a horizontal direction, because the pad oxide film 12 is removed with an isotropic etching. There may be formed a recess 26 composed of the semiconductor substrate 10 and the insulating layer 34.
An art is disclosed below in order to restrain a formation of the recess 26 in the first conventional embodiment. Japanese Patent Application Publication No. 11-145275 (hereinafter referred to as Document 1) discloses an art where the semiconductor substrate 10 is immersed in HF (hydrofluoric acid)/glycerol after the process of FIG. 1C and the silicon nitride film 14 is subjected to a side etching treatment as shown in FIG. 3. U.S. Pat. No. 5,521,422 (hereinafter referred to as Document 2) discloses an art where a sidewall composed of a silicon oxide film is formed on a side face of the opening portion 22 of the silicon nitride film 14 with a CVD method after the process of FIG. 1A.
In the art disclosed in Document 1, an etching speed of HF/glycerol with respect to the silicon nitride film 14 is large, being 4.1 nm/minute. It takes very small time, 2.4 minutes, to etch a silicon nitride film having a thickness of 10 nm. There may be variability in side etching amount L1 of the silicon nitride film 14 shown in FIG. 3 in a wafer or between wafers treated at a time. Controllability is not good when the silicon nitride film 14 is subjected to the side etching treatment, because the silicon nitride film 14 is side-etched and is backward. That is, there is a problem that controllability of a length L2 between each of the silicon nitride films 14 is not good.
On the other hand, there is a problem with respect to the art disclosed in Document 2. FIG. 1A illustrates the side face of the opening portion 22 of the silicon nitride film 14 being vertical to the surface of the semiconductor substrate 10. In actual, it is difficult that the silicon nitride film 14 is etched vertically. The side face of the opening portion 22 of the silicon nitride film 14 is therefore formed to be oblique to the surface of the semiconductor substrate 10 as shown in FIG. 4A. A silicon oxide film 15 may be formed so as to have a small thickness on the side face of the opening portion 22 as shown in FIG. 4B, if the silicon oxide film 15 is formed on the oblique silicon nitride film 14 with a CVD method. A width L3 of a sidewall 16 is therefore reduced as shown in FIG. 4C. There may be variability in an inclination of the side face of the opening portion 22 of the silicon nitride film 14 from the surface of the semiconductor substrate 10, in the wafer or between the wafers. There may be variability in the thickness of the silicon oxide film 15 on the side face of the opening portion 22. Further, there may be large variability in formation speed of the silicon oxide film 15 with respect to the CVD method. There may be larger variability in the thickness of the silicon oxide film 15 on the side face of the opening portion 22. The variability of the width L3 is larger in the wafer or between the wafers, if the sidewall 16 is formed as shown in FIG. 4C. That is, the controllability of a distance L2 between each of the silicon nitride films 14 is degraded.
As mentioned above, in the art disclosed in Document 1 and Document 2, the controllability of the distance L2 between each of the silicon nitride films 14 is not good. The controllability of the width of the insulating layer 34 of the STI may get worse if the controllability of the distance L2 between each of the silicon nitride films 14 is not good.